Current Reuse Gains UWB LNA

The proposed LNA is a two-stage amplifier with a current-reuse cascade common source structure, useful both for saving power consumption and maintaining good power gain. The two-stage design, initially targeted for power consumption of 6 mW from a +1-VDC supply, is shown in Fig. 1. This results in drain current of approximately 6 mA. Assuming a 6 mA current drawn by transistor M₁ for the first stage, the calculated size for transistor M₁ is approximately 150 μm based on Eq. 1⁸:

I_D ≈ 0.5μ_nC_ox(W/L)(V_GS1 – V_t)²   (1)

where:

V_GS1 = +0.7 VDC;

V_t = +0.5 VDC; and

μ_nC_ox = 369 μm for a typical 0.18-μm silicon CMOS semiconductor process.

The required transconductance, g_m1, can be determined by Eq. 2:

g_m1 = ∂I_DD/∂I_GS1 = μ_nC_ox(W/L) (V_GS1 – V_t)   (2)

Rearranging Eq. 1 to:

(V_GS1 – V_t = [2I_DD/μ_nC_ox(W/L)]^0.5

and substituting into Eq. 2, the equation for g_m1 can be simplified to Eq. 3:

g_m1 = [2μ_nC_ox(W/L)I_D]^0.5 = (2βI_D)^0.5   (3)

where β = μ_nC_ox(W/L) is known as the transconductance parameter. Hence, the calculated g_m1 is approximately 60.7 mA/V.

By ignoring the Miller effect of gate-drain capacitance (C_gd1) on transistor M₁, the input impedance of M₁ can be given by Eq. 4⁹:

Z_in1 = jω(L_g1 + L_s1) + (1/jωC_gs1 + g_m1L_s1/C_gs1   (4)

where:

g_m1 = the transconductance of M₁;   

C_gs1 = the gate-source capacitance of M₁;

L_s1 = the source degeneration inductor; and

L_g1 = the gate input inductor.   

The real part of the input impedance in Eq. 4 is given by Eq. 5:

ReZ_in1 = g_m1L_s1/C_gs1   (5)    

With given values of g_m1 and C_gs1, the desired impedance match to R_s (usually 50 Ω) can be obtained by setting L_s1 accordingly. The imaginary part of the input impedance can then be compensated with an input matching inductance, L_g1. The corresponding resonant frequency, ω₀, is approximated by Eq. 6:

ω₀ ≈ [1/(L_s1 + L_g1)C_gs1]^0.5   (6)

The source generation inductor, L_s1, is added for linearity and stability improvement, whereas the gate inductor L_g1 is needed for impedance matching between the source impedance and input of transistor M₁. In this design, the value of inductor L_s1 is chosen to be small enough (approximately 0.5 nH) so that it could be easily replaced by a bondwire inductance in order to reduce the chip area when necessary. Next, the value of gate inductor L_g1 is calculated from Eq. 6 to be approximately 1.5 nH using a resonant frequency of 5 GHz.

The current-reuse topology employs transistor M₂ stacked on top of the input transistor M₁ to save power consumption. The current-reuse function is implemented by L_d1, L_g2 and C_g2 to boost gain. Inductor L_g2 must form a series-resonant circuit with capacitance C_g2 and the input capacitance C_gs2 of transistor M₂ to create a low-impedance path to couple the output of M₁ to the input of M₂, while inductor L_d1 is chosen to be large enough to provide a high-impedance path to block the signal in the desired band.¹⁰ Parameter C_bp is a bypass capacitor. Therefore, the input can be amplified twice under this concurrent scheme.

It should be noted that the series resonant circuit consisting of L_g2 and C_g2 exhibits a narrowband characteristic. Consequently, the current-reuse function is maximized around the resonant frequency, which is designed to enhance the gain at the upper end of the desired frequency band. 

To achieve low power consumption, the width of transistor M₁ is set to 260 μm, while the width of M₂ is set to 200 μm. The inductances of L_d1 and L_g2 are 5.3 and 1.8 nH, respectively. Resistor R_b2 is used to provide bias voltage for transistor M₂. The inductor L_d2 (2.3 nH) and resistor R_d (54 Ω) are chosen to provide inductive peaking for extending the frequency range and providing peak gain at the center of the passband, achieving nearly flat overall wideband LNA gain. The last stage of the LNA consists of transistor M₃ and the current source is the 50-Ω buffer for measurement purposes. Capacitors C_in and C_out are DC blocks.

The current-reuse amplifier functions as a two-stage cascade amplifier. The noise figure of the second stage contributed by both the MOSFET (device M₂) and inductors L_g2 and L_d1 can be reduced by the gain of the first stage. With this design technique, not only is high gain possible, but low noise figure can be achieved simultaneously.

Figures 2 through 6 offer simulation results for the proposed UWB LNA for simulations performed with the SpectreRF simulation program from Cadence Design Systems, utilizing a 0.18-μm silicon CMOS semiconductor process from Taiwan Semiconductor Manufacturing Co. (TSMC). Figure 2 shows the small-signal S-parameters, where it can be seen that the UWB LNA achieves average simulated gain of 10.6 dB from 3 to 7 GHz, with gain flatness of better than 1.5 dB. The maximum gain of 12.3 dB occurs at 5 GHz.

Over the frequency range of interest, the input return loss (S₁₁) is less than 7.7 dB, while the output return loss (S₂₂) is less than 13 dB. The reverse isolation is less than -36 dB from 1 to 10 GHz, as shown in Fig. 3. The stability factor (K-factor) was also computed using S-parameter data and was found to be greater than 1 across the frequency range from 1 to 8 GHz (Fig. 4). This indicates that the proposed LNA is unconditionally stable across the frequency range of interest.

As Fig. 5 shows, the noise figure is better than 3.3 dB between 3 and 7 GHz with minimum noise figure of 2.6 dB at 4.3 GHz. The output power versus input power was measured for a single test tone at 5 GHz (Fig. 6), with a 1-dB compression point of about -10 dBm. The power consumption is only about 7 mW from a +1-VDC supply, which includes the power of the output buffer. 

The table summarizes the measured performance of the UWB LNA compared to previous works. The layout is shown in Fig. 7. The amplifier can achieve a wide bandwidth, high gain, and low noise figure while also operating with minimal power consumption—about 7 mW across a frequency range of 3 to 7 GHz.